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Transistor Matching, Differential Amplifiers - Final Exam Topics | CSE 60462, Exams of Computer Science

Material Type: Exam; Class: VLSI Circuit Design; Subject: Computer Science and Engr.; University: Notre Dame; Term: Unknown 1989;

Typology: Exams

2009/2010

Uploaded on 02/24/2010

koofers-user-6hn
koofers-user-6hn 🇺🇸

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Final Exam Topics
Final exam is Tuesday Dec. 15 from 4:15pm till 6:15pm, 356 Fitz.
Format: Similar to prior exams but with some questions being sets of multiple choice, true/false, very
short answer. Open book and notes but no electronic communication or computer. Bring a calculator.
Topics are from Exam 2 until now:
Analog Design W&H 12.6.1-12.6
Current Mirrors and Transistor Matching
Sample problem: design a current mirror with specified input and output currents
Differential Amplifiers
Common Source Amplifiers
MOS Transistor Small Signal Model
Source Followers
Operational Amplifiers
Analog simulation in Cadence
D/A converters W&H 12.6.7-12.6.9
Types of D/A converters: Understand both general circuit and layout considerations
Switch current,
R-2R Ladder,
Sigma Delta
Transistor matching
Creating “resistors”
Logic Synthesis and Place and Route in Cadence
Memories: W&H: 11.1-11.2.3, 11.3, 11.4-11.4.1
Array structure of memories
Cell arrays
Row decoders
Sense amps and column decode
Types of memory cells
ROM
SRAM – esp. “6T” cell
1T DRAM
Flash: NOR & NAND
Power W&H 4.4
Units: Joules, picoJoules and Watts
Sources of power in CMOS
Static: “Always there”
Subthreshold conduction, tunneling thru gate oxide, reverse bias leakage, ratioed logic
Be able to estimate static power for a chip based on transistor mix
Be able to estimate static power of ratioed logic
Dynamic: only when switch
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Final Exam Topics

Final exam is Tuesday Dec. 15 from 4:15pm till 6:15pm, 356 Fitz. Format: Similar to prior exams but with some questions being sets of multiple choice, true/false, very short answer. Open book and notes but no electronic communication or computer. Bring a calculator. Topics are from Exam 2 until now:

  • Analog Design W&H 12.6.1-12.
    • Current Mirrors and Transistor Matching
      • Sample problem: design a current mirror with specified input and output currents
    • Differential Amplifiers
    • Common Source Amplifiers
    • MOS Transistor Small Signal Model
    • Source Followers
    • Operational Amplifiers
    • Analog simulation in Cadence
  • D/A converters W&H 12.6.7-12.6.
    • Types of D/A converters: Understand both general circuit and layout considerations
      • Switch current,
      • R-2R Ladder,
      • Sigma Delta
    • Transistor matching
    • Creating “resistors”
  • Logic Synthesis and Place and Route in Cadence
  • Memories: W&H: 11.1-11.2.3, 11.3, 11.4-11.4.
    • Array structure of memories
      • Cell arrays
      • Row decoders
      • Sense amps and column decode
    • Types of memory cells
      • ROM
      • SRAM – esp. “6T” cell
      • 1T DRAM
      • Flash: NOR & NAND
  • Power W&H 4.
    • Units: Joules, picoJoules and Watts
    • Sources of power in CMOS
      • Static: “Always there”
        • Subthreshold conduction, tunneling thru gate oxide, reverse bias leakage, ratioed logic
        • Be able to estimate static power for a chip based on transistor mix
        • Be able to estimate static power of ratioed logic
      • Dynamic: only when switch
  • Load charge/discharge, short-circuit/Crowbar
  • KNOW THE EQUATION: αCFV^2
  • Be able to estimate dynamic power, esp. “per MHz”
  • Techniques for low power design
  • Reducing dynamic power
  • Reducing static power
  • Voltage and clock scaling
  • Wires W&H 4.5, 4.
  • Wire geometry
  • Computing resistance: resistivity, sheet resistance
  • Be able to compute resistance of a wire
  • Vias and contacts
  • Computing wire capacitance
  • Sources of capacitance: to above/below, to neighbors
  • Computing capacitance: parallel plates, dielectrics
  • Capacitance in different media: diffusion, polysilicon
  • Be able to compute capacitances
  • Lumped element models for RC effects in wires
  • Esp. ∏ model
  • Be able to construct 3-segment models
  • Be able to use Elmore delay model to compute RC delay thru wire
  • Crosstalk between pairs of neighboring wires
  • Sources and effects (noise and delay)
  • Aggressor and victim
  • Miller Coupling Factor
  • Variations in delay depending on signal correlation (victim is switching in same, different directions, undriven, stable)
  • Using repeaters to improve delay
  • Techniques for Crosstalk mitigation
  • Width
  • Spacing
  • Choice of layers
  • Shielding
  • Charge compensation
  • Twisted differential signaling
  • Effects on Logical Effort
  • Scaling
  • Moore’s Law
  • Scale Factor: what can change
  • Doping levels
  • Physical dimensions
  • Electrical parameters
  • Constant field scaling: E field strength across gate remains constant
  • Everything scales down by same factor
  • Gates get smaller in area by S^