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Material Type: Exam; Class: Electrical Engineering Design; Subject: Electrical Engineering; University: University of San Diego; Term: Fall 2004;
Typology: Exams
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Fall 2004 Church
Introduction:
The United States Naval Observatory Master Clock, located in Washington DC, is responsible for the keeping and transferring of time data for the United States. The Master Clock transfers the “master” time to eight remote substations located in undisclosed areas of the United States. Today, the transferring between the master clock and the remote substations is done one by one via satellite. At this time the master clock and each of the eight remote substations have one transmitter and one receiver.
Since time is transferred to each remote substation one by one, there is a slight inaccuracy of time at each station. This error, on the order of nanoseconds, is an error that can become burdensome in such things as 911 calls and naval applications. In our project, Modem Addressing Time Transfer (MATT), we will synchronize the time transferring event so the master clock transfers the time to all eight remote substations simultaneously. To do so, the master clock will need one transmitter and an eight channel receiver, while the eight remote substations will continue to have one transmitter and one receiver.
For our purpose MATT will not be used with a satellite; however, if SAIC wishes they will be able to make minor changes to our design allowing them to use MATT with a satellite network. SAIC provided us with some sample specifications, but ultimately they want a design that is flexible and can altered quite easily.
Problem Summary:
The task at hand was to design a modem (modulator/demodulator) capable of transmitting and receiving data. The transmitter system is responsible for modulating the data and sending it out and the receiver is responsible for demodulating and recovering the transmitted data. The modulation schemes are based on GPS technology. The system is also designed for complete future flexibility; such as altering transmission rates and bit resolutions can be accomplished with minimum effort.
Fall 2004 Church
Background Summary:
Time Keeping Background
The first monitoring of time was done with the sundial. As time progressed so did the way time was monitored. Time is now monitored, tracked, and transmitted by the US Naval Observatory.
The US Naval Observatory is responsible for the most accurate atomic clock system, the Master Clock. Accurate time information is essential in many aspects of military operations, navigation systems, and communications and intelligence fields.
To transfer time the most precisely and accurately the US Naval Observatory uses two-way satellite time transfer (TWSTT) between the master clock and 8 remote clocks around the US. The master clock and the 8 remote clocks each consist of one transmitter and one receiver. Two- way satellite time transfer allows an imprecision of less than 0.2 nanoseconds and an inaccuracy of about 1.0 nanosecond. This imprecision and inaccuracy may be the result of the single channel receiver at the master clock.
Market Background
SAIC has identified a small market for this type of technology, specifically in the government and defense sectors. Incidentally, SAIC plans on selling 10 units. These 10 units include the 8 substations, 1 main base station, and 1 spare.
Technical Survey:
Our project will require the following software for design and simulation:
Xilinx ISE 6.3i for VHDL code and project navigation XST or Synplicity for synthesis Aldec and ModelSim for simulation C software for PCI interface
The above software tools were accessible to us through SAIC and the University of San Diego’s engineering department. All team members have had experience with Xilinx, XST, C software, MatLab, and ModelSim. Our project required the following hardware for design:
Virtex II FPGA Board – (ADM-XRC-II) Analog Devices AD9772A Evaluation Board (14-bit DAC) Analog Devices AD9432 Evaluation Board (12-bit ADC) Micro-coax cables Computer
The above equipment was accessible to us through SAIC, where some of our lab work was completed. As a way to test the performance of the system, our project required the use of an oscilloscope and logic analyzer.
Fall 2004 Church
Figure 2: Mock-up System (Virtex-II FPGAs are located inside the computer)
Figure 3, shows the overall high-level system block diagram. Before transmission or reception could occur, certain control registers had to be initialized. Some examples of these control registers include such things that set-up carrier frequency, CDMA code sequences, and data channel enables. The registers, constants, and data was written directly to the FPGA from the PCI interface. Data was buffered in registers, and transmitted at a symbol rate of 250bps. The data was then modulated with the CDMA code sequences, which are at a rate of 1.023Mbps. The value of the data then relates to a certain phase shift in the carrier wave. The digital carrier wave, with QPSK modulation, was converted from a 8bit digital word, to an analog signal. The analog signal was transmitted via a coaxial cable to an ADC, which was converted back into a 8bit digital word. The receiver then used a correlator to match the phase of the carrier signal, and multiplied a matched carrier signal with that of the modulated one to obtain the Spread Spectrum modulated signal. The I-signal was then XOR’d with a matched CDMA I-sequence to obtain the original data. The data was then read from the FPGA and stored in a file on the computer, via the PCI interface. For a simultaneous multiple channel receiver, there would need to be basically multiple receivers instantiated in the FPGA, each with different CDMA sequences and phase correlations (this is not shown in Figure 3).
Fall 2004 Church
Figure 3: Overall System Block Diagram
Fall 2004 Church
FPGA System I/O :
Transmitter:
Inputs: o Clock (1bit) o Reset (1 bit) o Load (1 bit) o System Enable (1 bit) o Data Transmission Enable (1 bit) o I data (1 bit) o Doppler Shift Value (16 bits) o Carrier Phase ∆Frequency (16 bits) o Code Clock ∆Frequency (16 bits) o XBI: (13 bits) o XBQ: (13 bits) Outputs: o Modulated Signal Out (8 bits) o Clock out for DAC (1 bit)
Receiver:
Inputs: o Clock (1bit) o Reset (1 bit) o Load (1 bit) o System Enable (1 bit) o Data Rate (16 bits) o Doppler Shift Value (16 bits) o Carrier Phase ∆Frequency (16 bits) o Code Clock ∆Frequency (16 bits) o XBI: (13 bits) o XBQ: (13 bits) o I Demodulation Threshold (16 bits) o Q Demodulation Threshold (16 bits) o Phase Correlation Threshold (16 bits) o Accumulator Period (8 bits) o Code Correlator Period (12 bits) o Modulated Signal In (8 bits) Outputs: o Data received (1 bit) o System Ready (1 bit) o Clock out for ADC (1 bit)
Fall 2004 Church
Theory of Operation:
QPSK Modulation
For the Quadrature Phase Shift Key modulation scheme, two bits of data can be sent simultaneously. In our design, one channel is used to send data, and the other solely contains information about the CDMA code.
The I-channel, short for ‘in-phase,’ is made up of ± cos(ω); meanwhile the Q-channel, short for ‘Quadrature-phase,’ is made up of ± sin(ω). If the I-bit is ‘0’, then the I-channel transmits +cos(ω), and if the I-bit is ‘1’, then the I-channel transmits –cos(ω). Likewise, if the Q-bit is ‘0’, then the Q-channel transmits +sin(ω), and if the Q-bit is ‘1’, then the Q-channel transmits – sin(ω). The QPSK modulated signal then is made up by adding the I-channel with the Q-channel as seen in Table 1.
Table 1: QPSK Modulated Signal - I + Q
I Q I+Q (^) I+Q: cos( ω t + α )
0 0 cos(ω t ) + sin(ω t) 4 ) 2 cos(ω t +^7 π
0 1 cos(ω t ) - sin(ω t) 4 ) 2 cos(ω t +^1 π
(^1 0) -cos(ω t ) + sin(ω t) 4 ) 2 cos(ω t +^5 π
(^1 1) -cos(ω t ) - sin(ω t) 4 ) 2 cos(ω t +^3 π
So, if we are transmitting an I-sequence of 0..0..1..1, then the I-channel would look like:
Figure 4: I-channel sequence
Where, the black vertical lines represent the rising edges of the code clock (moments at which I&Q change). As you can see from Figure 4, the phase shifts by 180 º when the I sequence changes from ‘0’ to ‘1.’ The cosine term has a DC value of one added to it, because in our VHDL code we are working with unsigned positive binary numbers. Likewise, if we transmit a Q-sequence of 0..1..0..1 simultaneously with I, the Q-channel would look like:
Fall 2004 Church
Figure 7: QPSK signal multiplied by cosine and sine waves
To get the original I&Q data out of these two new signals we created, we accumulate the sequences for an accumulator period (with duration somewhere between the carrier and code periods) and make a decision based on a threshold value. The accumulate process is similar to that of an integrator. Figure 8 shows the signals accumulated for each code clock period. On the rising edge of the code clock we make a decision whether the data is zero or one by comparing the accumulated sum to a threshold value. The threshold value must be cleverly chosen to reflect the amplitude of the input signal, in this example it was set at 3500, which is approximately half- way between the high peak and low peak. As you can see, if the accumulated sum is greater than the threshold it corresponds to a ‘0’, and if the sum is less than the threshold, it corresponds to a ‘1’.
Figure 8: Accumulated signals
Fall 2004 Church
So, from using logic, we are able to obtain the I-sequence of 0..0..1..1, and the Q-sequence of 0..1..0..1. But since the threshold decision is made at the end of the accumulate process (which in this example was for 1 code clock period); the received data is delayed by one code clock cycle.
Phase Correlator For the demodulation process to work correctly, the phase of the sine and cosine terms used to demodulate the signal must be in sync with that of the phase of the input signal. Thus we need the following signals to be in sync, with matching phases θ: QPSK input = 2 cos( θ + β ) , where β is a discrete value corresponding to I&Q Cosine = cos( θ ) Sine = cos( θ + 3π/2 )
The correlation process basically has two steps; the first is to check if the generated phase matches that of the input phase, and the second step is to shift the generated phase until it does match. In this process we must assume that the frequencies of the input match that of the generated signal, which is a valid assumption since frequency shifts should be accounted for by the Doppler register in the phase generator.
Since the input signal is a quadrature-phase shifted signal, it is easiest to create a signal with phase shifts that match that of the input signal to use when correlating. Thus depending on the I&Q values (which must also be correlated), we shift the generated phase of a cosine wave appropriately as in Table 1. So in our example we are receiving a sequence of IQ equal to 00..01..10..11. Figure 9 shows the input signal and the generated signal, which will be used to correlate the phase. Notice that before the phase is correlated there will be a slight phase mismatch.
Figure 9: Input signal and the generated signal used for correlation with a slight phase offset.
To correlate the signal, again we take advantage of the multiply and accumulate process. We multiply the input signal by the generated signal and accumulate it over a certain period of time. The multiplication of the two terms will be greatest when the phase of the two signals match. At the end of the accumulation period, we have what we call our correlation number. If the correlation number is greater than a threshold, we know that the signal is phase correlated. If the correlation number falls short of the threshold, then we slightly shift the phase of the generated signal and run through the accumulation process until the phase does match. The amplitude difference between the input signal and the generated signal will play a role in setting an
Fall 2004 Church
Where α represents the amount of shift between the early and prompt, or late and prompt sequences.
Figure 11 shows the generated Q code, the time shifted early, prompt, and late codes, and received code. The generated Q code is 101100… The prompt code is delayed by exactly one code clock period, while the early code is delayed slightly less and the late code is delayed slightly more. The received code occurs after the prompt code but before the late code.
Figure 11: The signals used code correlation. The code is not matched in this figure.
To correlate the code sequence, we first exclusively-nor the received sequence with the early, late, and prompt sequences. What this does is output a ‘1’ if the two sequences match at that moment, and output a ‘0’ if they mismatch. Figure 12 shows the exclusive-nor of the early, prompt, and late sequences with the received sequence. As you can see from Figure 12, Pcorr has the least zeros, however for the code to be correlated we expect Pcorr to be a constant ‘1.’ It is also visible that Lcorr matches more than Ecorr.
Fall 2004 Church
Figure 12: Xnor of received Qcode and time shifted sequences.
To get a correlation number, we accumulate the three exclusively-nored sequences for a specified period of time. The prompt correlation number is then compared to the threshold, which is the number of clock cycles that we accumulated for. If the prompt correlation number does not match the threshold, then the code is mismatched and we compare the early and late correlation numbers to half the threshold value. If the early and late correlation numbers are less then ½ the threshold then we are most likely more than one code chip off of being correlated thus we will shift by one code chip. The direction of the shift doesn’t matter as long as it is consistent, since the code sequences will repeat every 1023 code chips (1ms). Otherwise if we are within one code chip we then compare the late correlation number to that of the early correlation number. Whichever correlation number is higher indicates in what direction to shift the generated signals. The generated code signals are shifted by shifting the code clock.
In this example, the x-axis is in terms of clock cycles, thus if we accumulate for 775 clock cycles, the prompt correlation number should be very close to 775 if the codes are matched. The correlation numbers in this example are as follows: Early correlation Number = 635 Prompt correlation Number = 735 Late correlation Number = 715 The prompt correlation number does not meet the threshold, thus we compare the late and early correlation numbers. Since the late correlation number is greater than the early correlation number, the code clock will be shifted accordingly and the generated I&Q signals will occur slightly later.
The xnor, compare, and shift processes are repeated until the prompt code matches the received code. Figure 13 shows the case when the received Q code sequence matches that of Qprompt.
Fall 2004 Church
Transmitter:
The transmitter block diagram in Figure 14, was implemented digitally in VHDL. It outputs a 8- bit parallel data stream containing the QPSK modulated signal with direct-sequence code spreading. The digital output was then converted to an analog signal through the use of an external DAC.
Figure 14: Transmitter Block Diagram
Carrier Phase Generator:
The Carrier Phase was generated through a technique of Direct Digital Synthesis (DDS) as in Figure 15. It generates phase values (0º to 360º) that repeat at a frequency of 5.115 MHz. It has two 16-bit accumulators, one which contains Doppler information (acceleration) and one that contains phase information (velocity). The carrier phase generator has two control registers: Doppler_Increment and Phase_Increment.
Fall 2004 Church
Figure 15: Phase Generator
The Doppler accumulator generates values that simulate ionspheric acceleration. In cases in which there is no Doppler effect, the Doppler increment is set to zero. The output frequency depends on the clock frequency, accumulator width and phase increment.
clk
Nbits out f
f 2
Thus, if we use 16-bit accumulators and a clock frequency of 100MHz, the required value for the phase increment (∆θ) as shown in Equation 1 is “0D18”H to produce a 5.115 MHz signal.
Code Clock:
The Code Clock generates the clock input for the CDMA code generator. The center nominal frequency of the code clock is 1.023 MHz. The Code Clock was generated in a DDS-type fashion, Figure 16, such that the transmitter can simulate ionspheric acceleration and the receiver can acknowledge this ionspheric acceleration. The most significant bit (MSB) from the phase accumulator is the code clock pulse. Thus, from Equation 1, if we use 16-bit accumulators and a clock frequency of 100 MHz, the required value for the phase increment (∆θ) is “029E”H to produce a 1.023 MHz signal.
Figure 16: Code Clock Generator
