Pipeline Organization and Data Hazards in Computer Architecture, Assignments of Computer Architecture and Organization

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Chapter 6:

Enhancing Performance with Pipelining

Overview of Pipelining

 Basic Philosophy

 Assembly Line Operations (factory)

 Goal

 Enhance Performance by increasing throughput

 Our Goal:

 Improve performance by increasing the instruction

throughput per clock cycle

Instructi on fetch Re g ALU Data Access Reg Instructi on fetch Re g ALU Data Access Reg Instructi on fetch Re g ALU Data Access Reg

Time^800 1600

lw $1, 100($0)

lw $2, 100($0)

lw $3, 100($0)

Prog. Exec. Order

Single Cycle Execution

Pipelined Execution

Instructi on fetch Reg ALU Data Access Reg Instructi on fetch Re g ALU Data Access Reg R e ALU Data Access Reg g

Instruct ion fetch

Time^800

lw $1, 100($0)

lw $2, 100($0)

lw $3, 100($0)

Prog. Exec. Order

Pipelining

 (^) What makes it easy?  (^) all MIPS instructions are the same length (fetch)  (^) just a few instruction formats ( rs, rt fields are invariant)  (^) memory operands appear only in loads and stores

 (^) What makes it hard?  (^) structural hazards: suppose we had only one memory  (^) control hazards: need to worry about branch instructions  (^) data hazards: an instruction depends on a previous instruction

 (^) We’ll talk about data hazard and forwarding, stalls and branch hazards

 (^) We’ll talk about exception handling

Pipelining

 Increases the number of simultaneous

executing instruction

 Increases the rate at which instructions are

executed

 Improves instruction throughput

 Information Flow:

 In general from Left to Right (1->2->3->4->5)

 The WB stage of step 5 writes data into register file

of the ID stage in step 2

 (^) 5 -> 2

 The MEM stage of step 4 controls the multiplexor

in the IF stage of step

 (^) 4 -> 1

A Pipelined Datapath

Five-stage Pipeline

Refer to Figure 6.9 for schematic illustrations

 Five stages are interconnected by 4 Pipeline

Registers (latches)

 Registers must be wide enough store information

A Pipelined Datapath

Five-stage Pipeline

IF ID EX MEM WB

IF/ID ID/EX EX/MEM MEM/WB

A Pipelined Datapath

Five-stage Pipeline

Time (in clock cycles)  --------------

lw $s3, 300 ($s0) IF ID EX MEM WB

lw $s2, 200 ($s0) IF ID EX MEM WB

lw $s1, 100 ($s0) IF ID EX MEM WB

CC1 CC2 CC3 CC4 CC5 CC6 CC

Inst.

1. IF stage: Fetches the first, second and third lw instructions in cycles CC1, CC2 and CC3 resp.

2. ID stage: Reads the rs register ($s0) for the first, second and third instructions in cycles

CC2, CC3 and CC4 respectively

4. EX stage: Calculates the memory address for the first, second and third instructions during clock cycles CC3, CC4, and CC5 respectively
5. MEM stage: Fetches memory words at addresses 100, 200, and 300 during clock cycles CC4, CC5, and CC6, respectively
6. WB stage: Copies the memory words into registers $s1, $s2, and $s3 during clock cycles CC5, CC6, and CC7, respectively

Each instruction execution takes 5 clock cycles in the pipeline

The 3 lw instructions take 7 clock cycles to execute

A Pipelined Datapath

Five-stage Pipeline Registers

IF/ID Latch: Holds fetched instruction and incremented PC

Allows the ID stage to decode instruction 1, while IF stage fetches instruction 2

ID/EX Latch: Stores the sign-extended immediate value and values fetched from register rs and rt Allows EX stage to utilize stored values, while the ID stage decodes Inst. 2 and the IF stage fetches register for instruction 3 EX/MEM Latch: Stores the branch target address, the ALU result, ALU output bit and value in the rt register Allows MEM stage to use stored values, while EX and ID stage execute the following instructions MEM/WB Latch: Stores ALU result and Data read from memory Allows WB stage to use stored data, while data memory fetches data for the following Instruction

Time (in clock cycles)  --------------

lw $s3, 300 ($s0) IF ID EX MEM WB

lw $s2, 200 ($s0) IF ID EX MEM WB

lw $s1, 100 ($s0) IF ID EX MEM WB

CC1 CC2 CC3 CC4 CC5 CC6 CC

Inst.

Announcement

 Your bonus questions will be due on Friday

(Dec. 16th) afternoon (5:00pm).

 Homework 5 will be due this Friday (Dec. 9th)

afternoon (5:00pm). You can expect the

homework solutions by next Monday night.

 Extra class: Dec 8th/Thursday from 5:15pm at

room 108!

 Final: Dec. 14th/Wednesday at 5:45pm at

room 115!

Review (1)

 Instruction execution can be broken down into five

stages

 (^) Instruction fetch (IF)  (^) Instruction decode and register fetch (ID)  (^) Execute (EX)  (^) Memory access (MEM)  (^) Write back (WB)

 Every instruction goes through all five stages

 Results are only written to the register file in WB

Hardware Usage

IM Reg ALU DM Reg

IM Reg ALU DM Reg

CC 1 CC 2 CC 3 CC 4 CC 5 CC 6 CC 7

Time (in clock cycles)

lw $ 2 , 200 ($ 0 )

lw $ 3 , 300 ($ 0 )

Program execution order (in instructions) lw $1, 100($0) IM Reg ALU DM Reg

Pipelined Datapath

In mstreumcotioryn

Address

4

32

0

Add (^) resultAdd left 2Shift

Instruction

IF/ID EX/MEM MEM/WB

M u x

0 1

Add

PC

0

Address

Write data

M u x

Registers 1

data 1Read data 2Read

Read register 1 Read register 2

(^16) Sign extend

Write register Write data

Read data memoryData 1

resultALU M u x

ALUZero

ID/EX