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11

ASIC Design

2

 Computational

 Integral with physical processes

 sensors

 Reactive

 at the speed of the environment

 Heterogeneous

 hardware/software, mixed architectures

 Networked

 shared, adaptive

Embedded Computing Systems (Cyber-Physical Systems)

Typical SOC Core Sizes 2017/9/27 4

SOC : System-on-Chip  SoC Design Trends (communication centric design) The architecture is tightly coupled

DMA CPU DSP

Mem Ctrl. Bridge MPEG I o o The “Board-on-a-Chip” Approach C System Bus Control Wires (^) Peripheral Bus  Bus based interconnect  Low cost  Easier to Implement  Flexible

Design Representations

 Technology-independent

Hardware Description Language

(HDL)

 Technology-dependent netlist

consisting of nets connecting

elements from the vendor’s design

library

 Physical implementation in which

the elements in the netlist are

physically placed on the die and

interconnected by various layers

of wiring

8 Performance

10 Variation  The extreme variability of the individual devices, up to ±20%.  In addition, the device properties often vary between each processed semiconductor wafer.  Slight changes to the amount of diffusion time, uneven doping levels, etc. can have large effects on device properties.

11 Variation

1313 Design Methodologies Design Complexity Design Productivity 1975 1980 1985 1990 1995 2000 Gates High level SPICE Pattern Generation IC CAD ASICs Place & Route Logic Simulation Logic Synthesis Behavioral Synthesis Cycle-Based Simulation Design Reuse Deep Submicron System on a Chip Transistors Polygons

1414 System Level Design Investment of People & Money System Level Design Physical Design Functional Design Functional Verification Some will move to: physical design   system level Designer population and budgets will shift

1616 A Typical ASIC Design Flow Floorplan Macro placement Signal Integrity Check & repair Timing Driven Routing Timing Driven Placement Physical Libs Pinout Timing Constraints DRC/LVS Mask Data Gen Extraction & Delay Calc STA and/or Timing Simulation sdf Formal Verification

NETLIST

Mask Data to FAB Back-End Part Clock Tree Synthesis

Design Flow Comparison ASIC (^) FPGA

RTL Synthesis Flow 9/27/2017 19

Physical Synthesis Flow 9/27/2017 20