Computer Architecture Instruction Set Architecture, Lecture Slide - Computer Science, Slides of Computer Architecture and Organization

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Randal E. Bryant

Carnegie Mellon University

CS:APP2e

CS:APP Chapter 4

Computer Architecture

Instruction Set

Architecture

http://csapp.cs.cmu.edu

• 2 – CS:APP2e Instruction Set Architecture Assembly Language View  Processor state

 Registers, memory, …

 Instructions

 addl, pushl, ret, …

 How instructions are encoded

as bytes

Layer of Abstraction  Above: how to program machine

 Processor executes instructions

in a sequence

 Below: what needs to be built

 Use variety of tricks to make it

run fast

 E.g., execute multiple

instructions simultaneously

ISA

Compiler OS

CPU

Design

Circuit

Design

Chip

Layout

Application

Program

Y86 Instruction Set #

Byte^0 1 2 3 4

pushl rA A (^0) rA 8 jXX Dest (^7) fn Dest popl rA B (^0) rA 8 call Dest (^8 0) Dest cmovXX rA, rB (^2) fn rA rB irmovl V, rB (^3 0 8) rB V rmmovl rA, D(rB) (^4 0) rA rB D mrmovl D(rB), rA (^5 0) rA rB D OPl rA, rB (^6) fn rA rB ret 9 0 nop 1 0 halt 0 0

Y86 Instructions Format  1 – 6 bytes of information read from memory

 Can determine instruction length from first byte

 Not as many instruction types, and simpler encoding than with

IA

 Each accesses and modifies some part(s) of the program state

Y86 Instruction Set #

Byte^0 1 2 3 4

pushl rA A (^0) rA 8 jXX Dest (^7) fn Dest popl rA B (^0) rA 8 call Dest (^8 0) Dest cmovXX rA, rB (^2) fn rA rB irmovl V, rB (^3 0 8) rB V rmmovl rA, D(rB) (^4 0) rA rB D mrmovl D(rB), rA (^5 0) rA rB D OPl rA, rB (^6) fn rA rB ret 9 0 nop 1 0 halt 0 0 addl 6 0 subl 6 1 andl 6 2 xorl 6 3

Y86 Instruction Set #

Byte^0 1 2 3 4

pushl rA A (^0) rA 8 jXX Dest (^7) fn Dest popl rA B (^0) rA 8 call Dest (^8 0) Dest rrmovl rA, rB (^2) fn rA rB irmovl V, rB (^3 0 8) rB V rmmovl rA, D(rB) (^4 0) rA rB D mrmovl D(rB), rA (^5 0) rA rB D OPl rA, rB (^6) fn rA rB ret 9 0 nop 1 0 halt 0 0 jmp 7 0 jle 7 1 jl 7 2 je 7 3 jne 7 4 jge 7 5 jg 7 6

Instruction Example Addition Instruction  Add value in register rA to that in register rB

 Store result in register rB

 Note that Y86 only allows addition to be applied to register data

 Set condition codes based on result  e.g., addl %eax,%esi Encoding: 60 06  Two-byte encoding

 First indicates instruction type

 Second gives source and destination registers

addl rA, rB 6 0 rA rB

Encoded Representation

Generic Form

Arithmetic and Logical Operations  Refer to generically as “OPl”  Encodings differ only by “function code”

 Low-order 4 bytes in first

instruction word

 Set condition codes as side effect

addl rA, rB 6 0 rA rB

subl rA, rB 6 1 rA rB

andl rA, rB 6 2 rA rB

xorl rA, rB 6 3 rA rB

Add

Subtract (rA from rB)

And

Exclusive-Or

Instruction Code Function Code

Move Instruction Examples

movl $0xabcd, %edx irmovl $0xabcd, %edx 30 82 cd ab 00 00

IA32 Y86 Encoding

movl %esp, %ebx rrmovl %esp, %ebx 20 43

movl -12(%ebp),%ecx mrmovl -12(%ebp),%ecx 50 15 f4 ff ff ff

movl %esi,0x41c(%esp) rmmovl %esi,0x41c(%esp)

movl $0xabcd, (%eax) —

movl %eax, 12(%eax,%edx) —

movl (%ebp,%eax,4),%ecx —

40 64 1c 04 00 00

Conditional Move Instructions  Refer to generically as “cmovXX”  Encodings differ only by “function code”  Based on values of condition codes  Variants of rrmovl instruction

 (Conditionally) copy value

from source to destination

register

rrmovl rA, rB

Move Unconditionally

cmovle rA, rB

Move When Less or Equal

cmovl rA, rB

Move When Less

cmove rA, rB

Move When Equal

cmovne rA, rB

Move When Not Equal

cmovge rA, rB

Move When Greater or Equal

cmovg rA, rB

Move When Greater

2 0 rA rB

2 1 rA rB

2 2 rA rB

2 3 rA rB

2 4 rA rB

2 5 rA rB

2 6 rA rB

Y86 Program Stack  Region of memory holding program data  Used in Y86 (and IA32) for supporting procedure calls  Stack top indicated by %esp

 Address of top stack element

 Stack grows toward lower addresses

 Top element is at highest

address in the stack

 When pushing, must first

decrement stack pointer

 After popping, increment stack

pointer

%esp

Increasing

Addresses

Stack “Top”

Stack

“Bottom”

Stack Operations  Decrement %esp by 4  Store word from rA to memory at %esp  Like IA  Read word from memory at %esp  Save in rA  Increment %esp by 4  Like IA

pushl rA A 0 rA F

popl rA B 0 rA F

Miscellaneous Instructions  Don’t do anything  Stop executing instructions  IA32 has comparable instruction, but can’t execute it in user mode  We will use it to stop the simulator  Encoding ensures that program hitting memory initialized to zero will halt

nop 1 0

halt 0 0

Status Conditions

Mnemonic Code

ADR 3

Mnemonic Code

INS 4

Mnemonic Code

HLT 2

Mnemonic Code

AOK 1

 Normal operation  Halt instruction encountered  Bad address (either instruction or data) encountered  Invalid instruction encountered Desired Behavior  If AOK, keep going  Otherwise, stop program execution