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Understanding the Von Neumann Model of Computer Architecture, Exams of Architecture

An overview of the Von Neumann Model of computer architecture, which is a fundamental concept in modern computing. The model describes how a computer processes instructions and data using a single shared memory. the history of early computers, the components of the Von Neumann Model, and the basic operations of loading, storing, and fetching instructions. It also explains the role of the control unit and the execution of instructions.

What you will learn

  • What are the basic operations of loading, storing, and fetching instructions in the Von Neumann Model?
  • What are the components of the Von Neumann Model?
  • How does the control unit work in the Von Neumann Model?
  • How does the Von Neumann Model differ from other computer architectures?
  • What is the Von Neumann Model of computer architecture?

Typology: Exams

2021/2022

Uploaded on 09/27/2022

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1
Chapter 4
The Von Neumann
Model
Based on slides © Mc Graw-Hill
Additional material © 2004/2005 Lewis/Martin
4-2
CSE 240
Warning!
This is a bottom-up course
No secrets, no magic
e.g., gates build on transistors, logic c ircuits from gates, e tc.
But… This is a top-down lecture
You’ll have to trust m e for a couple slides
Start with very a bstract discussion of computer architectur e
Meet with Chapter 3 m aterial soon
4-3
CSE 240
What Do We Know?
A LOT!!
Data representation (binary, 2’s complement, floating point, …)
Transistors (p-type, n-type, CMOS)
Gates (complementary logic)
Combinational logic c ircuits (PLAs), memory (latches, flip-flops, …)
Sequential logic circu its (state machines)
Simple “process ors” (programmable traffic sign)
What’s next?
Apply all this to tradit ional computing
Software interface: in structions
Hardware implementa tion: data path
4-4
CSE 240
A Little Context
1943: ENIAC
First general electronic computer (Pre sper Eckert and John Mauchly)
(Or was it Atananasoff i n 1939? Or Konrad Zuse in 1941?)
18,000 tubes (had to replace 50 a day!)
Memory: 20 10-digit numbers (decimal)
Hard-wired program (via dials, switches,
and cables)
Completed in 1946
1944: Beginnings of E DVAC
Among other improvements, includes program sto red in memory
Gave birth to UNIVAC-I (1951)
Completed in 1952
See Eniac by Scott McCartney
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pf4
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Download Understanding the Von Neumann Model of Computer Architecture and more Exams Architecture in PDF only on Docsity!

Chapter 4

The Von Neumann

Model

Based on slides © McGraw-Hill Additional material © 2004/2005 Lewis/Martin CSE 240 4- 2

Warning!

This is a bottom-up course

  • No secrets, no magic e.g., gates build on transistors, logic circuits from gates, etc****.

But… This is a top-down lecture

  • You’ll have to trust me for a couple slides
  • Start with very abstract discussion of computer architecture
  • Meet with Chapter 3 material soon CSE 240 4- 3

What Do We Know?

A LOT!!

  • Data representation (binary, 2’s complement, floating point, …)
  • Transistors (p-type, n-type, CMOS)
  • Gates (complementary logic)
  • Combinational logic circuits (PLAs) , memory (latches, flip-flops, …)
  • Sequential logic circuits (state machines)
  • Simple “processors” (programmable traffic sign)

What’s next?

  • Apply all this to traditional computing
  • Software interface: instructions
  • Hardware implementation: data path CSE 240 4- 4

A Little Context

1943: ENIAC

  • First general electronic computer (Presper Eckert and John Mauchly) (Or was it Atananasoff in 1939? Or Konrad Zuse in 1941?)
  • 18,000 tubes (had to replace 50 a day!)
  • Memory: 20 10-digit numbers (decimal)
  • Hard-wired program (via dials, switches, and cables)
  • Completed in 1946 1944: Beginnings of EDVAC
  • Among other improvements, includes program stored in memory
  • Gave birth to UNIVAC-I (1951)
  • Completed in 1952 See Eniac by Scott McCartney

CSE 240 4- 5

Aside: Early Memories

Mercury delay

lines!

Q’ Q

1 0 M E R C U R Y Output Input Speaker “Microphone” CSE 240 4- 6 Context Continued: Stored Program Computer 1945: John von Neumann

  • First Draft of a Report on EDVAC See John von Neumann and the Origins of Modern Computing by William Aspray Von Neumann Machine (or Model)
  • Memory , containing instructions and data
  • Control unit , for interpreting instructions
  • Processing unit , for performing arithmetic and logical operations
  • Input/Output units , for interacting with real world CSE 240 4- 7 Von Neumann Model MEMORY MAR MDR INPUT Keyboard Mouse Scanner Disk

OUTPUT

Monitor Printer LED Disk

PROCESSING UNIT

ALU TEMP

CONTROL UNIT

PC IR

CSE 240 4- 8

Memory

k x m array of stored bits ( k is usually 2 n )

Address

  • Unique ( n -bit) identifier of location

Contents

  • m -bit value stored in location

Basic Operations

  • Load: read a value from a memory location
  • Store: write a value to a memory location - • - 0000 0001 0010 0011 0100 0101 0110 1101 1110 1111 00101101 10100010

CSE 240 4- 13

LC- CSE 240 4- 14 One More Gate

Tri-state buffer

  • NOT an inverter!

Allows wires to be “shared”

  • Alternative to mux
  • Only one source may drive at a time!

D Q

E

0 1 Z

0 0 Z

E D Q

Z = “high impedance” state

(no current, i.e., no “pressure”)

CSE 240 4- 15

Instructions

Fundamental unit of work

Constituents

  • Opcode : operation to be performed
  • Operands : data/locations to be used for operation

Encoded as a sequence of bits (just like data!)

  • Sometimes have a fixed length ( e.g., 16 or 32 bits)
  • Control unit interprets instructionGenerates control signals to carry out operation
  • Atomic: operation is either executed completely, or not at all

Instruction Set Architecture (ISA)

  • Computer’s instructions, their formats, their behaviors CSE 240 4- 16 Example: LC-3 ADD Instruction

LC-3 has 16-bit instructions

  • Each instruction has a four-bit opcode, bits [15:12]

LC-3 has eight registers (R0-R7) for temporary storage

  • Sources and destination of ADD are registers

“Add the contents of R2 to the contents of R6,

and store the result in R6.”

CSE 240 4- 17

Example: LC-3 LDR Instruction

Reads data from memory

Base + offset addressing mode

  • Add offset to base register to produce memory address
  • Load from memory address into destination register

“Add the value 6 to the contents of R3 to form a

memory address. Load the contents of memory

at that address and place the resulting data in R2.”

CSE 240 4- 18

Instruction Processing

Question

  • How are instructions executed?

DECODE instruction

EVALUATE ADDRESS

FETCH OPERANDS

EXECUTE operation

STORE result

FETCH instruction from mem.

CSE 240 4- 19

Instruction Processing: FETCH

Idea

  • Put next instruction in IR & increment PC

Steps

  • Load contents of PC into MAR
  • Increment PC
  • Send “read” signal to memory
  • Read contents of MDR, store in IR

Who makes all this happen?

  • Control unit

EA

OP

EX

S

F

D

CSE 240 4- 20

FETCH in LC- Load PC into MDR (inc PC)

Control

Data

CSE 240 4- 25

Instruction Processing: EVALUATE ADDRESS

Compute address

  • For loads and stores
  • For control-flow instructions (more later)

Examples

  • Add offset to base register (as in LDR)
  • Add offset to PC (as in LD and BR)

EA

OP

EX

S

F

D

CSE 240 4- 26

EVALUATE ADDRESS in LC-

Load/Store

CSE 240 4- 27

Instruction Processing: FETCH OPERANDS

Get source operands for operation

Examples

  • Read data from register file (ADD)
  • Load data from memory (LDR)

EA

OP

EX

S

F

D

CSE 240 4- 28

FETCH OPERANDS in LC-

ADD

CSE 240 4- 29

FETCH OPERANDS in LC-

LDR

CSE 240 4- 30

Instruction Processing: EXECUTE

Actually perform operation

Examples

  • Send operands to ALU and assert ADD signal
  • Do nothing ( e.g., for loads and stores)

EA

OP

EX

S

F

D

CSE 240 4- 31

EXECUTE in LC-

ADD

CSE 240 4- 32

Instruction Processing: STORE

Write results to destination

  • Register or memory

Examples

  • Result of ADD is placed in destination reg.
  • Result of load instruction placed in destination reg.
  • For store instruction, place data in memorySet MDRAssert WRITE signal to memory

EA

OP

EX

S

F

D

CSE 240 4- 37

Changing the Sequence of Instructions

Recall FETCH

  • Increment PC by 1

What if we don’t want linear execution?

  • E.g., loop, if-then, function call

Need instructions that change PC

  • Jumps are unconditionalAlways change the PC
  • Branches are conditionalChange the PC only if some condition is true e.g., the contents of a register is zero CSE 240 4- 38 Example: LC-3 JMP Instruction

Set the PC to the value of a register

  • Fetch next instruction from this address

“Load the contents of register R3 into the PC.”

0 0 0 0 0 0 0 0 0 0 0 0 CSE 240 4- 39 How Does Control Unit Work? CSE 240 4- 40 Remember Finite State Machines? State Machine Combinational Logic Circuit Storage Elements

Inputs Outputs

State Next state Current state PC,IR Control signals

CSE 240 4- 41

Control Unit Details

Finite state machine

  • Input: PC, IR
  • Output: many control signals

Need to map abstract ops

to control signals

  • E.g., MAR <- PCGatePC and LD.MAR
  • E.g., PC <- PC + 1PCMUX=2 and LD.PC

LC-

  • 35 states (Fig. C.2) CSE 240 4- 42 Instruction Processing Summary Instructions look just like data
  • Interpreted by machine (or software) Three basic kinds of instructions
  • Computational instructions (ADD, AND, …)
  • Data movement instructions (LD, ST, …)
  • Control instructions (JMP, BRnz, …) Six basic phases of instruction processing F → D → EA → OP → EX → S
  • Not all phases are needed by every instruction
  • Multiple phases per cycle possible
  • Phases may take variable number of machine cycles CSE 240 4- 43 Alternate Implementation Execute Each Instruction in Single Cycle
  • Much simpler
  • All phases happen in one cycle          CSE 240 4- 44 Single-Cycle Implementation (ADD)          ADD 0001 0 I[8:6] I[2:0] I[11:9] 1 00 00 0 1 0 1 Instr I[15:12] I[5]        Opcode Control

CSE 240 4- 49

Next Time

Lecture

• LC-

Reading

  • Chapter 5 - 5.

Quiz

  • Online!

Upcoming

  • Homework due Monday 11 October