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CSCI 4717 – Computer Architecture Buses – Page 1
CSCI 4717/
Computer Architecture
Topic: Buses
Reading: Stallings, Sections 3.4, 3.5, and 7.
CSCI 4717 – Computer Architecture Buses – Page 2
Buses – Common Characteristics
- Multiple devices communicating over a single set of wires
- Only one device can talk at a time or the message is garbled
- Each line or wire of a bus can at any one time contain a single binary digit. Over time, however, a sequence of binary digits may be transferred
- These lines may and often do send information in parallel
- A computer system may contain a number of different buses
CSCI 4717 – Computer Architecture Buses – Page 3
Buses – Structure
- Serial versus parallel
- Around 50-100 lines although it's possible
to have as few as 3 or 4
- Lines can be classified into one of four
groups
- Data lines
- Address Lines
- Control Lines
- Power
CSCI 4717 – Computer Architecture Buses – Page 4
Buses – Structure (continued)
- Bus lines (parallel)
- Data
- Address
- Control
- Power
- Bus lines (serial)
- Data, address, and control are sequentially sent down single wire
- There may be additional control lines
- Power
CSCI 4717 – Computer Architecture Buses – Page 5
Buses – Structure (continued)
- Data Lines
- Passes data back and forth
- Number of lines represents width
- Address lines
- Designates location of source or destination
- Width of address bus specifies maximum memory capacity
- High order selects module and low order selects a location within the module
CSCI 4717 – Computer Architecture Buses – Page 6
Bus Structure – Control lines
- Because multiple devices communicate on a line, control is needed
- Timing
- Typical lines include:
- Memory Read or Write
- I/O Read or Write
- Transfer ACK
- Bus request
- Bus grant
- Interrupt request
- Interrupt acknowledgement
- Clock
- Reset
CSCI 4717 – Computer Architecture Buses – Page 7
Operation – Sending Data
- Obtain the use of the bus
- Transfer the data via the bus
- Possible acknowledgement
CSCI 4717 – Computer Architecture Buses – Page 8
Operation – Requesting Data
- Obtain the use of the bus
- Transfer the data request via the bus
- Wait for other module to send data
- Possible acknowledgement
CSCI 4717 – Computer Architecture Buses – Page 9
Classic Bus Arrangement
- All components attached to bus (STD bus)
- Due to Moore's law, more and more functionality exists on a single board, so major components are now on same board or even the same chip
CSCI 4717 – Computer Architecture Buses – Page 10
Physical Implementations
- Parallel lines on circuit
boards (ISA or PCI)
CSCI 4717 – Computer Architecture Buses – Page 11
Physical Implementations (continued)
mother boards (PC104)
Firewire)
CSCI 4717 – Computer Architecture Buses – Page 12
Single Bus Problems
Lots of devices on one bus leads to:
- Physically long buses
- Propagation delays – Long data paths mean that co- ordination of bus use can adversely affect performance
- Reflections/termination problems
- Aggregate data transfer approaches bus capacity
- Slower devices dictate the maximum bus speed
CSCI 4717 – Computer Architecture Buses – Page 19
Bus Types
Dedicated vs. Time Multiplexed
- Dedicated
- Separate data & address lines
- Time multiplexed
- Shared lines
- Address valid or data valid control line
- Advantage - fewer lines
- Disadvantages
- More complex control
- Degradation of performance
CSCI 4717 – Computer Architecture Buses – Page 20
Bus Types Physical Dedication
- Physically separating buses and controlling them with a "channel changer“
- Advantages – faster
- Disadvantages – physically larger
CSCI 4717 – Computer Architecture Buses – Page 21
Bus Arbitration
- Listening to the bus is not usually a
problem
- Talking on the bus is a problem – need
arbitration to allow more than one module
to control the bus at one time
- Arbitration may be centralised or
distributed
CSCI 4717 – Computer Architecture Buses – Page 22
Centralised vs. Distributed Arbitration
- Centralised Arbitration
- Single hardware device controlling bus access – Bus Controller/Arbiter
- May be part of CPU or separate
- Distributed Arbitration
- Each module may claim the bus
- Access control logic is on all modules
- Modules work together to control bus
CSCI 4717 – Computer Architecture Buses – Page 23
Bus Timing
- Co-ordination of events on bus
- Synchronous – controlled by a clock
- Asynchronous – timing is handled by well-
defined specifications, i.e., a response is
delivered within a specified time after a
request
CSCI 4717 – Computer Architecture Buses – Page 24
Synchronous Bus Timing
- Events determined by clock signals
- Control Bus includes clock line
- A single 1-0 cycle is a bus cycle
- All devices can read clock line
- Usually sync on leading/rising edge
- Usually a single cycle for an event
- Analogy – Orchestra conductor with baton
- Usually stricter in terms of its timing
requirements
CSCI 4717 – Computer Architecture Buses – Page 25
Synchronous Bus Timing
CSCI 4717 – Computer Architecture Buses – Page 26
Asynchronous Timing
- Devices must have certain tolerances to
provide responses to signal stimuli
- More flexible allowing slower devices to
communicate on same bus with faster
devices.
- Performance of faster devices, however, is
limited to speed of bus
CSCI 4717 – Computer Architecture Buses – Page 27
Asynchronous Timing – Read
CSCI 4717 – Computer Architecture Buses – Page 28
Asynchronous Timing – Write
CSCI 4717 – Computer Architecture Buses – Page 29
Bus Width
- Wider the bus the better the data transfer
rate or the wider the addressable memory
space
- Serial “width” is determined by
length/duration of frame
CSCI 4717 – Computer Architecture Buses – Page 30
Peripheral Component Interconnection (PCI) Bus
Brief history
- Original PC came out with 8-bit ISA bus which was slow, but had enormous amount of existing equipment.
- For AT, IBM expanded ISA bus to 16-bit by adding connector
- Many PC board manufacturers started making higher speed, proprietary buses
- Intel released the patents to its PCI and this soon took over as the standard
CSCI 4717 – Computer Architecture Buses – Page 37
PCI Transaction Types (continued)
- Memory write – writing 1 or more cycles to memory
- Memory write and invalidate – writing 1 or more cycles to memory allowing for cache write-back policy
- Configuration read – reading PCI device's configuration (up to 256 configuration registers per device)
- Configuration write – writing PCI device's configuration (up to 256 configuration registers per device)
- Dual address cycle – indication of 64-bit addressing on 32 bit lines
CSCI 4717 – Computer Architecture Buses – Page 38
PCI Read Timing Diagram
CSCI 4717 – Computer Architecture Buses – Page 39
PCI Bus Arbiter
CSCI 4717 – Computer Architecture Buses – Page 40
PCI Bus Arbitration Between Two Masters
CSCI 4717 – Computer Architecture Buses – Page 41
Higher Performance External Buses
- Historically, parallel has been used for high speed peripherals (e.g., SCSI, parallel port zip drives rather than serial port). High speed serial, however, has begun to replace this need
- Serial communication also used to be restricted to point-to-point communications. Now there's an increasing prevalence of multipoint
CSCI 4717 – Computer Architecture Buses – Page 42
IEEE 1394 FireWire
- Inexpensive alternative needed for SCSI
- High performance serial bus
- Serial implies cheaper cabling (fewer wires, less shielding, less synchronization)
- Small connectors for smaller devices
- Fast
- Low cost
- Easy to implement
- Also being used in digital cameras, VCRs and TVs
CSCI 4717 – Computer Architecture Buses – Page 43
FireWire Configuration
- Daisy chain/tree structure (Mac O/S Help
indicates that daisy chain is preference for
up to 16 devices)
- Up to 63 devices on single port – really 64
of which one is the interface itself
- Up to 1022 buses can be connected with
bridges
- Automatic configuration for addressing
- No bus terminators
- Hot swappable
CSCI 4717 – Computer Architecture Buses – Page 44
FireWire 3 Layer Stack
CSCI 4717 – Computer Architecture Buses – Page 45
FireWire 3 Layer Stack Physical Layer
- Transmission medium, electrical and
signaling characteristics
- Up to 400 Mbps
- Arbitration – basic form
- Fair arbitration
- Urgent arbitration
- Link layer packet transmission
CSCI 4717 – Computer Architecture Buses – Page 46
Arbitration – Basic form
- Upon automatic configuration, each tree designates a root
- Parent/child relationship forms tree topology
- Root acts as central arbitrator
- Requests are first-come-first-serve
- Simultaneous requests are granted first to the closest node to the root and second to the lower ID number
- Two additional functions are used to best allocate the use of the bus - Fair arbitration - Urgent arbitration
CSCI 4717 – Computer Architecture Buses – Page 47
Fair arbitration
- Keeps one device from monopolizing the bus by allowing only one request during a set fairness interval
- At beginning of interval, all devices set arbitration_enable flag
- Each device may compete for bus access
- If bus access is granted, arbitration_enable flag is cleared prohibiting bus access until next fairness interval
CSCI 4717 – Computer Architecture Buses – Page 48
Urgent arbitration
- Allows overriding of fairness interval by
nodes configured as having an urgent
priority
- Provides support for devices with severe
latency requirements or high throughput
such as video
- They may use the bus up to 75% of the
time, i.e., for each non-urgent packet,
three urgent packets may be sent
