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ECE 4110 - Sequential Logic Design Exam, Fall 2004, Exams of Electrical and Electronics Engineering

Tennessee Technological University (TTU)Electrical and Electronics Engineering

The instructions and questions for the final exam of the ece 4110 - sequential logic design course, offered in the fall 2004 semester. The exam covers topics such as designing a binary counter using 74xxx components, verifying timing conditions in synchronous sequential logic circuits, and implementing a finite state machine (fsm) using vhdl.

Typology: Exams

Pre 2010

Uploaded on 07/30/2009

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ECE 4110 - Sequential Logic Design
Final Exam - Fall 2004
NOTES:
• Closed book
• Calculator and 3 sheets of handwritten notes allowed
• Do not make any marks on the 74xx component pinout sheet handout
• Read the problems CAREFULLY!
• Watch the details
• Draw and write NEATLY
• Show ALL your work for full credit
• Give a single answer to each question
• Wherever possible, box your answers
• Label each answer with the problem number and part letter
• Keep your work and answers together
• Put all work and answers on your paper
• Write with a pencil, not a pen
• Either erase or clearly mark out things I should ignore in grading
• Use ONE SIDE of the paper, standard 8 1/2 x 11 inches
• Put each problem's work and answer on a SEPARATE page
• Attach all pages in the given problem order, with this question sheet on top, with
YOUR NAME on it
• Please ASK if you have any questions about the exam
1. [25 pts] Design a free-running binary counter, modulo-11, using a minimal number of
standard 74xxx MSI and SSI packages, selected from the component pinout sheet
handout. It must have the counting sequence 3, 4, 5, ..., 12, 13 and repeating. The starting
state upon power-up should be 3, assuming the existence of a PWRUP_L signal that
pulses true during system power up. Draw a proper bubble-to-bubble schematic,
including all part numbers and MSI pin names, and label the counter outputs Q0 (LSB)
through Qn (MSB). You must briefly explain its operation.
2. [25 pts] Give the equations that are used to verify proper timing conditions in a
synchronous sequential logic circuit, and carefully define each term in the equations. If
you were to discover that your circuit violated any of the desired conditions, describe all
possible solutions to fix each of the problems.
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ECE 4110 - Sequential Logic Design

Final Exam - Fall 2004

NOTES:

  • Closed book
  • Calculator and 3 sheets of handwritten notes allowed
  • Do not make any marks on the 74xx component pinout sheet handout
  • Read the problems CAREFULLY!
  • Watch the details
  • Draw and write NEATLY
  • Show ALL your work for full credit
  • Give a single answer to each question
  • Wherever possible, box your answers
  • Label each answer with the problem number and part letter
  • Keep your work and answers together
  • Put all work and answers on your paper
  • Write with a pencil, not a pen
  • Either erase or clearly mark out things I should ignore in grading
  • Use ONE SIDE of the paper, standard 8 1/2 x 11 inches
  • Put each problem's work and answer on a SEPARATE page
  • Attach all pages in the given problem order, with this question sheet on top, with YOUR NAME on it
  • Please ASK if you have any questions about the exam
  1. [25 pts] Design a free-running binary counter, modulo-11, using a minimal number of standard 74xxx MSI and SSI packages, selected from the component pinout sheet handout. It must have the counting sequence 3, 4, 5, ..., 12, 13 and repeating. The starting state upon power-up should be 3, assuming the existence of a PWRUP_L signal that pulses true during system power up. Draw a proper bubble-to-bubble schematic, including all part numbers and MSI pin names, and label the counter outputs Q0 (LSB) through Qn (MSB). You must briefly explain its operation.
  2. [25 pts] Give the equations that are used to verify proper timing conditions in a synchronous sequential logic circuit, and carefully define each term in the equations. If you were to discover that your circuit violated any of the desired conditions, describe all possible solutions to fix each of the problems.
  1. [30 pts total] Complete the implementation of a minimal-cost FSM that satisfies the following state/output table. The FSM should start in state Init after power-up.

a. Convert this table to a standard transition/output list , with fully simplified expressions and the minimal number of transitions. As usual, group all the same current states consecutively in the list. b. Write the complete VHDL architecture section, in the Two Process FSM style , using a minimal amount of code. The VHDL entity section is given below. Use the default (simplest) state assignment provided by Quartus. States must change on the positive edge of the clock. No explicit reset function is needed. Follow our standard VHDL style for names, keywords, and indentation.

| N |

S0 1
InitInit,00 Go1 ,01
Go1Go22,01 Go22,01
Go22Go1 ,10 Init,11

S*,XY LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY fsm IS PORT ( n, clk: IN STD_LOGIC; x, y : OUT STD_LOGIC ) ; END fsm ;

  1. [20 pts] Based on the following diagram of the Xilinx XC4000 FPGA configurable logic block (CLB):

a. Describe the implementation (what is the internal logic structure?) and the functionality (what does it do?) provided by the block labeled F. b. How many input signals and output signals exist in the CLB? (2 answers here) c. Output X can be a function of which input signals? d. What are the signal choices available to drive the flip-flop clock inputs? e. What are the signal choices available to drive the flip-flop clock enable inputs?