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ENGR 160 HW #8: Timing Diagrams & D Flip-Flops, Assignments of Microelectronic Circuits

The instructions and problems for homework #8 in engr 160 digital circuits course at eastern washington university. Students are required to complete timing diagrams for a given digital circuit and a master-slave configured d flip-flop.

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Pre 2010

Uploaded on 08/16/2009

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Fall 2008
ENGR 160 – DIGITAL CIRCUITS
Section 1
Department of Engineering & Design at Eastern Washington University
HOMEWORK #8
DUE: TUESDAY, November 25, 2008, in my office by 5pm
Note: Please be extremely neat in your timing diagrams!
1. Consider the following circuit:
Complete the following timing diagram.
C
D
R
S
Q
Q'
pf2

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Fall 2008

ENGR 160 – DIGITAL CIRCUITS

Section 1 Department of Engineering & Design at Eastern Washington University HOMEWORK #

DUE: TUESDAY , November 25, 2008, in my office by 5pm

Note: Please be extremely neat in your timing diagrams!

  1. Consider the following circuit: Complete the following timing diagram. C D R S Q Q'
  1. Consider the master-slave configured D flip flop discussed in class. Complete the following timing diagram for it.: C D Y Q Q' Where Y is the output of the master D-latch driving the slave D-latch.
  2. How does the timing diagram in 2 compare to the timing diagram in 1? Can you draw any conclusions?