Prctice Problems for Final Exam
Computer Architecture CSCI 320 – Fall 2007
December 3, 2007
Practice Problems for Final Exam Included are some questions from old CS320 quizes and final
exams. I promise at least one of these will be on the exam.
1. (10 pts) Describe the difference between reliability and availability.
2. (10 pts) How are precise interrupts defined?
3. (10 pts) A processor issues 10 disk I/Os per second. The average disk service time is 40 ms.
Assume requests are exponentialy distributed and FIFO.
a). On average, how utilized is the disk?
b). What is the average time spent in the queue?
c). What is the average response time for a disk request including the queuing time and disk service
time?
d). What is the average length of the waiting line?
e). What is the average number of tasks in service?
4. (15 pts) You are given a 6-stage pipeline where each stage takes 2 nanoseconds. Assuming you
have 10 items to be processed, what is the speedup of the pipeline over the serial case?
5. (10 pts) Explain the mechanism of a “delayed branch” used in some RISC architectures. Give
an example to demonstrate the concept. Explain why it is used.
6. (15 pts) Assume a CPU sends 15 disk I/O requests per second (exponentially distributed).
Assume the average disk service time is 20 ms and the average time spent in the queue is 5 ms.
a). On average, what is the utilization of the disk?
b). What is the length of the queue? (Hint: Use John Little’s Law.)
7. (20 pts) A memory has 2 words per block, 32-bit words and is word addressable. An address is
32 bits wide. The write-through cache is direct mapped and has 8 cache lines. The write policy is
write allocate. Given the following code sequence:
Address Instruction Comments
------- ----------- --------
0 Load R1, 7 Load the contents of address 7 into R1
1 Add R1, 8 Add the contents of address 8 to R1
2 Store R1, 9 Store the contents of R1 into address 9
3 Load R2, 18 Load the contents of address 18 into R2
4 Add R2, 19 Add the contents of address 19 to R2
5 Store R2, 20 Store the contents of R2 into address 20
6 Halt
1
